Sapsol Technologies INC 7

Asics Engineer

United States

Sponsorship not specifiedDetected 2 days ago

PythonCadenceCommunication

About the role

please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC, PSV, Diagnosys, Pattern Retargeting, Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT
Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical

Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
DFT SDC creation and DFT timing closure support.
Boundary scan, iJTAG, SSN, and design-for-debug methodologies.

Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.

Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
Act as a technical escalation point for advanced DFT and post-silicon debug issues.
Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
Required Skills & Qualifications Strong hands-on experience in ASIC DFT with end-to-end ownership.
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.

Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
ATPG simulations and fault coverage debug.

This listing is sourced directly from Sapsol Technologies INC 7's careers page and normalized into a canonical job model.