Altera

Altera

Senior Director, Silicon Architecture and Design Engineering (Ethernet/PCIe Center of Excellence))

San Jose, California, United States · Director

Sponsorship not specified$232k-$341kDetected 3 days ago
NegotiationFPGAElectrical EngineeringLeadership

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odds of building a lasting career here

61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

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Files H-1B transfers

13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

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About the role

  • The role is Altera's technical authority for Ethernet across business units, leading a global silicon team.
  • Managed RTL, verification, DFT, emulation, implementation, bring-up, and validation teams.
  • Provide technical leadership for networking datapath architecture, including packet processing, L2/L3 forwarding, QoS, traffic management, buffering, scheduling, congestion management, and telemetry.

Responsibilities

  • Lead, grow, and mentor a high-performing silicon engineering organization delivering complex FPGA, ASIC, and SoC products across Altera's programmable portfolio.
  • Own end-to-end silicon execution from product definition and microarchitecture. Managed RTL, verification, DFT, emulation, implementation, bring-up, and validation teams.
  • Define and drive Ethernet architecture across MAC, PCS, FEC, Auto-Negotiation, Link Training, and high-speed PHY/SerDes integration for current and future product generations.
  • Drive large, complex silicon programs: planning, resource alignment, milestone tracking, and risk management against aggressive performance, quality, cost, and schedule targets.
  • Partner with architecture, software, systems, product planning, and manufacturing to turn product requirements into executable silicon roadmaps, and represent silicon engineering in executive reviews.
  • Lead cross-functional decisions on architectural tradeoffs, hard/soft IP partitioning, and internal-versus-third-party Ethernet IP strategy across throughput, latency, bandwidth, congestion behavior, PPA, cost, manufacturability, and schedule.
  • Engage foundry, IP, and EDA partners, and drive methodology, automation, and KPI-based improvements in quality, predictability, and velocity.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, and 15+ years in silicon engineering, ASIC, SoC, or FPGA product development.
  • 10+ years in networking and Ethernet technologies, including architecture, silicon development, or product development for networking, switching, interconnect, or data center infrastructure.
  • Deep expertise in IEEE 802.3 Ethernet architecture, from MAC/PCS through high-speed PHY/SerDes integration.
  • We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
  • Applicants must be eligible for any required U.S. export authorizations.
  • 10+ years leading or working across the silicon development lifecycle, from architecture and RTL through verification, DFT, emulation, physical design, post-silicon validation, and production.

Nice to have

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
  • Experience leading silicon development at advanced process nodes, delivering high-complexity SoCs or ASICs into production, and standing up new teams.
  • Experience with emerging 1.6T Ethernet and 112G/224G-class SerDes, and with FPGA or heterogeneous SoC platforms, including Ethernet IP, transceiver integration, and third-party PHY/controller IP.
  • Shift 1 (United States of America)
  • San Jose, California, United States
  • Posting Statement:
  • Experience with multiple generations of high-speed Ethernet through 800G-class, plus AI/data center scale-out networking (RDMA/RoCE, lossless Ethernet, congestion control, or Ultra Ethernet).

Skills

  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $231,500 - $341,075 USD

Company info

  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • Represent Altera externally with hyperscale, networking, and AI infrastructure customers, ecosystem partners, and standards bodies (IEEE 802.3, Ultra Ethernet Consortium, OIF), translating that engagement into Ethernet IP requirements and reference designs.
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