Astera Labs Inc.
Principal Mixed Analog Design Engineer
Irvine, California, United States · Principal
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$3,326 more — $173,326 — moves this role to Level IV and 4 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $173,326 would place this position at wage Level IV. That figure is within the posted range, and I'd like to target it. This role classifies under "Electrical Engineers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electrical Engineers (17-2071) · Los Angeles-Long Beach-Anaheim, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Your work directly shapes the performance, power, and reliability of products deployed in the world's most advanced data centers.
- This is a high-impact, hands-on role at a hyper-growth company purpose-built for AI connectivity.
- If you want your circuits to enable the next generation of AI compute, this is where that happens.
Responsibilities
- Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.
- Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.
- Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.
- Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.
- Define and execute test plans to correlate silicon performance against design targets.
- Set analog design methodology, review standards, and best practices across the team.
- Partner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions.
- Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it.
- As a Principal Analog Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O - the silicon building blocks that move data at the speed AI demands.
- You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale.
Requirements
- 8+ years of experience in analog and mixed-signal integrated circuit design.
- Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.
- Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
- Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.
Nice to have
- Excellent communication skills and a collaborative, ownership-driven mindset.
Skills
- Analog & Mixed-Signal Design
- Silicon Execution & Validation
- Technical Leadership
- Mentor and guide junior engineers, elevating the technical capability of the analog organization.
Compensation
- Salary range is $170,000 to $210,000 depending on experience, level, and business need.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.