Cerebras Systems
Senior ASIC RTL Design Engineer, AI Hardware
Sunnyvale, CA · Senior
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$18,899 more — $218,899 — moves this role to Level IV and 4 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $218,899 would place this position at wage Level IV. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- As a senior front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE).
- This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions.
- You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.
Responsibilities
- Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
- Work closely with PD team members for design closure to meet PPA goals.
- Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
Requirements
- Master's degree in Computer Science, Electrical Engineering, or equivalent.
- 8+ years of experience in delivering complex, high performance high quality RTL designs.
- Experience with Front End Chip integration and third-party IP integration.
Nice to have
- Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.
Skills
- Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups.
Compensation
- The base salary range for this position is $200,000 to $290,000 annually.
Benefits
- Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
- Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning or related fields.
Company info
- Build a breakthrough AI platform beyond the constraints of the GPU.
- Publish and open source their cutting-edge AI research.
- Work on one of the fastest AI supercomputers in the world.
- Enjoy job stability with startup vitality.
- Our simple, non-corporate work culture that respects individual beliefs.
This listing is sourced directly from Cerebras Systems's careers page and normalized into a canonical job model.