Intel
Design Verification Architect
US, California, Folsom
Sponsorship not specified$164k-$232kDetected 1 day ago
GitVerilogProblem Solving
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odds of building a lasting career here
56Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role70
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
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About the role
- Integrates block testbenches in chip-level UVM environments and verifies integration.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
Responsibilities
- Define, architect, and document verification strategy and methodologies for implementing and verifying pre-silicon design in the most optimal manner
- Architect testbenches and develop Universal Verification Methodology (UVM) or formal-based verification approaches
- Develop test strategy, testbench architecture, and test plans for design blocks to conform to specifications
- Enable interaction with analog and digital teams and support post-silicon validation activities
- Results-driven, with the ability to drive optimal solutions between analog and digital designs
Requirements
- Bachelor's degree with 10+ years of relevant industry experience, or a Master's degree in a related field with 8+ years of relevant industry experience
- You must have 8+ years of experience with/in:
Nice to have
- DDR design domain knowledge with strong understanding of DFI/DDR/LPDDR protocols
- Experience with VSCode, GitHub Copilot, or any other AI-assisted development tools
- Experience to Formal Property Verification and Git version control
- are required to be initially considered for this position.
- are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Compensation
- Range for jobs which could be performed in the US: $164,470.00-232,190.00 USD
- The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Annual Salary Range for jobs which could be performed in the US:
- $164,470.00-232,190.00 USD
Benefits
- Find out more about the benefits of working at Intel.
- Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.
- Collaborate with architecture and design teams to create random test generation plans, run functional simulations to identify gaps in design specifications, and conduct failure analysis, coverage analysis, and closure
- Define and develop the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage
Company info
- We offer a total compensation package that ranks among the best in the industry.
This listing is sourced directly from Intel's careers page and normalized into a canonical job model.