Ambarella Corp.
Sr. Memory Validation Engineer
US Headquarters · Senior · Full-time
Sponsorship not specified$152k-$179kDetected 31 days ago
PythonMachine LearningData AnalysisStatisticsTest Automation
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61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
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About the role
- Memory is where a lot of system-level problems come to die.
- Marginal timing, a corner-case power state transition, a customer platform that fails one boot in ten thousand - these issues are expensive to reproduce, slow to root-cause, and they tend to come back.
- This is a role for someone who likes both the oscilloscope and the dataframe.
Responsibilities
- Own the memory training and calibration code. You'll develop, maintain, and tune the training and calibration routines that get LPDDR5/5X and LPDDR6 running reliably at speed across parts, boards, and operating conditions.
- Influence future silicon. Propose architectural and design enhancements for next-generation memory controllers, backed by empirical data, customer feedback, and field experience.
- Validate power-saving features, characterizing them against performance, reliability, and power targets across a wide range of real-world use cases.
- Support silicon bring-up, qualification, and production readiness for memory subsystems.
- What you'll build
- Beyond closing individual issues, this role exists to create durable leverage:
Requirements
- Hands-on experience with LPDDR5/5X and LPDDR6, and working familiarity with the relevant JEDEC specifications
Nice to have
- Silicon bring-up or post-silicon validation experience on a production program
- Experience with low-power state validation (self-refresh, power-down, DVFS-style transitions)
- Statistical analysis, ML, or dashboarding experience applied to hardware validation data
- Firmware or driver-level exposure to the memory stack
- Signal integrity fundamentals: eye diagrams, jitter, and timing margin analysis on high-speed interfaces
- Running memory at state-of-the-art speeds is genuinely hard, and it gets harder every generation.
- The margins shrink while the variables multiply: load, power, temperature, process spread.
- Silicon doesn't behave the way the simulations said it would, so the work becomes finding calibration and training approaches that hold up on real parts, in real systems, across the full operating envelope.
Skills
- Comfort with data at scale - you can take a pile of shmoo, margining, or regression results and find the signal in it
Compensation
- The base salary range is $152,000 - $179,000.
Benefits
- Build automation for memory stability testing, performance characterization, speed binning, and regression analysis - expanding test coverage while cutting cycle time.
Company info
- It also comes with real visibility: the data you produce goes to the architects planning the next generation, the field teams supporting customers today, and the validation teams qualifying silicon tomorrow.
- Faster root-cause analysis and issue closure - which customers feel directly
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This listing is sourced directly from Ambarella Corp.'s careers page and normalized into a canonical job model.