PsiQuantum
Senior Analog / Mixed-Signal IC Design Engineer
Palo Alto, California, United States · Senior · Full-time
Sponsorship not specified$145k-$165kDetected 156 days ago
AlgorithmsCadenceVerilogEMI/EMCElectrical EngineeringCommunicationOrganizational Skills
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odds of building a lasting career here
53Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role74
Entry-level history0
PERM / green-card track0
Lottery odds (Level III)83
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~45% per draw at Level III). Good if you win; have a cap-exempt backup on your list.
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About the role
- We are seeking an experienced Analog/Mixed-Signal IC Design Engineer to design and deliver high-performance integrated circuits from concept through silicon validation and production.
- This role spans architecture, circuit design, and lab bring-up, with significant ownership and direct impact on real products.
Responsibilities
- Define system architecture and drive trade-offs across noise, linearity, power, area, and bandwidth.
- Perform transistor-level design, simulation, and optimization using industry-standard tools.
- Develop behavioral models (Verilog-A / SystemVerilog RNM) for system-level verification and architectural exploration.
- Work closely with layout to ensure performance through parasitic-aware design and careful floorplanning.
- Collaborate with digital and verification teams for robust mixed-signal integration.
- Drive/manage silicon bring-up, debug, and lab characterization.
- Drive clear design documentation and participate in design reviews.
- Take ownership of deliverables and drive work to completion, including under tight timelines.
Requirements
- Proven experience designing and taping out analog or mixed-signal ICs.
- Proficiency with SPICE-based simulation tools (e.g., Spectre, HSPICE).
- MS or PhD in Electrical Engineering or related field.
- Strong fundamentals in analog circuit design and device physics.
- Expertise in CMOS or SiGe design across one or more process nodes.
- Deep understanding of noise, mismatch, stability, and nonlinearity.
- Ability to design from first principles and solve complex circuit problems creatively.
- Strong organizational skills to manage large design spaces (corners, Monte Carlo, trade-offs).
- Demonstrated ownership mindset with a focus on delivering high-quality result.
Nice to have
- Experience with data converters, RF/analog front-ends, or high-speed interfaces.
- Experience with both mature and advanced process nodes (FinFET or beyond) a plus.
- Hands-on experience with silicon validation and lab debugging.
- Experience contributing across full chip development cycles.
- Experience with Cadence Virtuoso design environment.
- Hands-on experience with layout, tapeout, and bench validation.
- Familiarity with SystemVerilog RNM and/or Verilog-A modeling.
- First-principles thinking and strong engineering judgment.
Compensation
- $145,000 - $165,000 USD
- Bay Area Pay Range
- $180,000 - $197,000 USD
Company info
- Note: PsiQuantum will only reach out to you using an official PsiQuantum email address and will never ask you for bank account information as part of the interview process.
- We are not accepting unsolicited resumes from employment agencies.
Visa & Work Authorization
- g pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domesti
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This listing is sourced directly from PsiQuantum's careers page and normalized into a canonical job model.