Eliyan Corporation
DV - Staff Verification Engineer - Serdes
Bay Area, Vancouver or Toronto · Staff+
Sponsorship not specifiedDetected 106 days ago
VerilogSignal ProcessingLeadership
About the role
- This is a hands-on technical leadership role.
- You will work with a cross-functional team of experts.
Responsibilities
- Develop and execute verification plans for Serdes, other PHYs, DSP blocks, TX/RX equalization and CDR.
- Create and maintain SystemVerilog/UVM-based verification environments
- Maintain regression environments
- Collaborate with design team to ensure design quality
- Develop, maintain, and track various test plan items and progress towards RTL freeze
Skills
- Join the leading chiplet startup!
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