Nuvacore
CPU Clock Distribution and Custom Clock Design
Santa Clara, CA · Senior · Full-time
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About the role
- Architect and drive the end-to-end clock generation and distribution methodology using H-tree, mesh, spine, and multi-source clock-tree synthesis for high-frequency CPU cores, co-optimizing skew, insertion delay, jitter, duty-cycle distortion, and clock power.
- As a Custom Clock Design and Distribution (CCD) Engineer, you will participate in the following:
- Partner with PLL/FLL, timing, power, CAD, physical design, and DFT teams aligning clock source models, jitter budgets, and power-aware clocking and drive Tools, Flows and Methodology (TFM), including clock-analysis automation and team-wide best practices.
Responsibilities
- Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads.
- As a member of the CPU clock design team, you will architect and deliver the clock generation and distribution networks that set the frequency, skew, jitter, and power ceiling for the product.
- Design and characterize custom clock circuits at "transistor level": clock buffers and repeaters, dividers, deskew and duty-cycle correction, clock-gating and clock-mux cells meeting PPA targets across PVT corners.
- Own end-to-end clock-network closure: SPICE-driven skew, latency, and jitter analysis, EM/IR and signal-integrity signoff on the clock grid, and STA correlation (OCV/AOCV/POCV) across Functional and DFT modes.
Requirements
- Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in clock design, clock distribution, and/or custom circuit design.
- Hands-on transistor-level design experience with clock dividers, deskew and duty-cycle correction, clock-gating and mux cells at advanced CMOS nodes.
- Proven experience constructing and analyzing low-skew, low-power clock distribution networks using H-tree, mesh, spine, and multi-source CTS for high-frequency CPUs.
- Demonstrated track record delivering clock networks and/or clocking IP through tape-out, with silicon-validated PPA - frequency, skew, jitter, and power - in high-volume products.
- Proficiency with PLL/FLL specifications, clock source modeling, skew estimation, jitter budgeting, and jitter/duty-cycle measurement.
- Experience with power-aware clocking - clock gating, DVFS, clock-skipping, and resonant or mesh-based clocking strategies for clock-power reduction.
- Experience with testchip clock development and benchmarking, and partnering directly with foundries on PDK bring-up and clock-device co-optimization (DTCO) at leading-edge nodes.
- Experience using Agentic AI tools for productivity and automation.
Compensation
- $140k-$250k
This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.