Astera Labs Inc.
Senior Digital Design Engineer
Toronto, Ontario, Canada · Senior
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About the role
- You will contribute across architecture, micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe and Ethernet controllers, bridges, switches, and related SerDes interfaces.
- Your work will span block-level and full-chip development at advanced process nodes and help enable reliable, high-bandwidth connections among CPUs, GPUs, memory, storage, and networking devices in rack-scale AI systems.
- You will help improve product quality, accelerate time to market, and strengthen customer confidence in every release.
Responsibilities
- Develop micro-architecture and implement synthesizable RTL for high-performance PCIe or Ethernet controllers, bridges, switches, and SerDes-related IP.
- Translate architecture and protocol requirements into scalable designs using SystemVerilog and Verilog.
- Own block-level and full-chip design deliverables from specification through implementation and GDS handoff.
- Contribute to designs at advanced process nodes of 16 nm or smaller, including PCIe Gen 6/7, UALink, or UCI-based connectivity where applicable.
- Integrate controller, SerDes, processor, peripheral, and other IP while partnering with RTL, physical design, DFT, verification, and firmware teams.
- Drive synthesis, timing analysis, timing closure, clock-domain crossing, lint, and design-quality reviews.
- Support gate-level simulation, emulation, and pre-silicon and post-silicon design implementation activities.
- Collaborate with verification and system teams to assess verification completeness, debug design issues, and close implementation gaps.
- Partner with firmware and embedded software teams to define and validate hardware-software interfaces.
- Use Synopsys and Cadence design and analysis tools, along with Python or Perl scripting, to improve design productivity and automation.
Skills
- Digital Architecture and RTL Implementation
- Integration, Timing, and Design Quality
- Contribute to top-level integration, floor-planning discussions, PAD planning, and DFT implementation.
- Cross-Functional Execution and Debug
- Communicate technical status, risks, and tradeoffs clearly while managing multiple priorities with appropriate ownership and urgency.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.