Ambiq Micro, Inc.
Sr. Staff Engineer - DFT
Austin, Texas, United States · Staff+
No sponsorshipDetected 6 days ago
PythonCadenceElectrical EngineeringMedical DevicesResearchCommunicationProblem Solving
About the role
- If that's you, join us - the intelligence everywhere revolution starts here.
- This role will be on-site 5 days a week in NW Austin.
- No new H-1B sponsorship is available for this role.
Responsibilities
- Develop and implement low-power DFT architecture and infrastructure.
- Perform pre/post-layout scan and MBIST simulations.
- Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling.
- Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore.
- We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.
- This role involves collaborating with design, verification, and manufacturing teams to ensure products meet testability, yield, and quality objectives.
Requirements
- BS/MS in Electrical Engineering, Electronics Engineering, or related field with 10+ years of DFT implementation experience.
- Hands-on expertise with Cadence Genus and Modus Compression for low-power scan insertion and ATPG pattern generation (required).
- Strong knowledge of DFT methodologies, including scan (stuck-at, at-speed, path-delay), scan compression, boundary scan, and MBIST.
- Proven experience defining and implementing hierarchical DFT architectures for complex SoCs.
- Expertise in Low-Power DFT, MBIST implementation, and memory test strategies.Experience generating, validating, and deploying memory repair patterns using the Tessent MBIST flow.
- Experience analyzing ATE failure data and performing diagnosis using ATPG tools.
- Visa/Work Authorization: Candidates must be authorized to work in the U.S. We welcome applicants with valid EAD work authorization and may consider H-1B transfers for candidates with an approved I-140.
- Strong background in test coverage, test time analysis, and optimization for scan and MBIST patterns.
- Experience collaborating with test engineering teams to develop and bring up production test programs.
- Solid understanding of timing analysis and constraint development.
- Experience developing ATPG and MBIST testbenches and performing pre-/post-layout simulations.
- Working knowledge of RTL design and verification.
Nice to have
- Proficiency in Tcl
- experience with Perl and/or Python preferred.
- Experience with gate-level simulation (GLS) preferred.
Benefits
- Generate structural test vectors, analyze, and improve coverage, test time, and test cost.
- Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.
- The successful candidate will own the DFT strategy, develop test methodologies, and drive continuous improvement in test coverage and manufacturing efficiency.
Company info
- Ambiq is on a mission to enable intelligence everywhere - powering the AI edge revolution with the world's lowest-power semiconductor solutions.
- We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.
- We are seeking an experienced DFT (Design for Testability) Engineer to design, implement, and optimize test architectures for semiconductor products.
Visa & Work Authorization
- Candidates must be authorized to work in the U.S. We welcome applicants with valid EAD work authorization and may consider H-1B transfers for candidates with an approved I-140.
- No new H-1B sponsorship is available for this role.
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