River
Member of Technical Staff, Hardware, Physical Design Engineer
Palo Alto, CA; Austin, TX · Staff+
H1B sponsorship available$200k-$420kDetected 25 days ago
PythonMachine LearningDeep LearningLogisticsElectrical Engineering
About the role
- We are looking for exceptional physical design engineers to transform our high-performance architectural concepts into production-ready silicon.
- You will own the physical implementation flow from synthesis through tape-out, pushing the absolute limits of advanced foundry nodes to maximize PPA.
- You will take ownership of block-level and top-level physical design, collaborating tightly with RTL designers to close timing, electrical, and physical verification for our custom AI accelerator.
Responsibilities
- Drive Synthesis and Place-and-Route: Own the physical implementation flow from RTL synthesis through placement, clock tree synthesis (CTS), and routing for high-performance blocks.
- Maximize PPA: Optimize layout topologies to maximize cell density and utilization, architecting robust power delivery networks (PDN) to minimize IR drop and meet aggressive frequency targets on advanced foundry nodes.
- Execute Physical Verification: Run and debug sign-off physical verification, including Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Antenna rule compliance.
- Co-Design with RTL: Partner directly with the RTL team to provide early physical feedback on logic structures, pipeline depth, and routing congestion to streamline implementation closure.
- Advance Flow Automation: Integrate and develop next-generation AI-driven EDA tools and workflows to fundamentally accelerate the physical implementation cycle and optimize design closure.
- Proven track record running logic synthesis, integrating compiled memory macros, and managing multi-voltage design techniques using power intent specifications (UPF/CPF).
- Exceptional debugging skills with a first-principles approach to navigating complex trade-offs between congestion, timing slack, and power density in highly utilized designs.
- A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with RTL and architecture teams.
- Own the physical implementation flow from RTL synthesis through placement, clock tree synthesis (CTS), and routing for high-performance blocks.
Requirements
- Bachelor's degree in Electrical Engineering or Computer Engineering, and 5+ years practical industry experience working with advanced process nodes (7nm or below).
- Deep hands-on proficiency with industry-standard physical design, timing, and sign-off tools (e.g., Innovus, Fusion Compiler, PrimeTime, RedHawk).
Nice to have
- (We encourage you to apply even if you don't meet all of these)
- An extensive track record of delivering high-performance SoCs, CPUs, GPUs, or AI accelerators through multiple successful production tape-outs.
- Hands-on experience optimizing physical layouts for highly parallel compute structures, such as systolic arrays, large tensor execution units, or high-bandwidth memory (HBM) interfaces.
- Visa Sponsorship: We sponsor visas and are committed to supporting the process for the right candidate.
Skills
- Skills and Qualifications
Compensation
- Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD.
Benefits
- River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.
Company info
- We are scientists, engineers, and builders from the industry's top tech companies and AI labs.
- We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.
- At River, our mission is to create personal AI owned and shaped by each individual.
- personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.
Visa & Work Authorization
- We sponsor visas and are committed to supporting the process for the right candidate.
This listing is sourced directly from River's careers page and normalized into a canonical job model.