Astera Labs Inc.
Principal Physical Design Engineer -EMIR & Power Integrity
San Jose, California, United States · Principal
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$2,408 more — $187,408 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $187,408 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Astera Labs is scaling the connectivity fabric behind the world's largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship.
- This role is fully on-site at our San Jose, CA location.
Responsibilities
- Own static and dynamic IR drop and electromigration analysis at block and full-chip levels, driving closure to foundry sign-off criteria
- Drive UPF-based power domain planning and power-aware sign-off across multi-voltage designs
- Analyze thermal and current density issues and recommend design modifications to ensure long-term reliability
- Collaborate with package, power grid, and floorplan teams to identify and resolve voltage drop hotspots and EM violations early in the design cycle
- Partner with RTL, STA, verification, IP vendors, and foundry to drive power integrity convergence through tapeout
- Develop and refine EMIR runsets, stimulus methodologies, and reporting dashboards to improve predictability and reduce iterations
- Build and maintain EMIR analysis flows and automation infrastructure for efficient multi-corner analysis
- Deliver clear, actionable root-cause analysis and mitigation guidance at both block and full-chip levels
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 8+ years of experience in IR drop, electromigration analysis, and power integrity sign-off for complex SoCs at advanced nodes (7nm and below)
- Proficiency with Cadence Voltus and/or Synopsys RedHawk-SC / PrimeTime PX
Nice to have
- Master's degree in Electrical Engineering or a related field
- Package-level power delivery analysis / co-simulation, including advanced packaging or multi-die integration exposure
Skills
- Power Integrity Analysis & Sign-off
- Design Convergence & Cross-Functional Partnership
- Provide actionable feedback to implementation teams on power grid reinforcement, decap strategy, and hard-macro / SerDes integration
- Methodology & Automation
Compensation
- Base salary range is $185,000 to $240,000 depending on experience, level, and business need.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.