Astera Labs Inc.
Principal/ Sr.Principal Digital Design Engineer
San Jose, California, United States · Principal
Sponsorship not specified$185k-$230kDetected 27 days ago
CadenceEmbedded SystemsElectrical EngineeringLeadershipCollaboration
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odds of building a lasting career here
64Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
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Files H-1B transfers
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About the role
- Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.
- This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers.
- Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions.
Responsibilities
- Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
- Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
- Drive designs to production, ensuring accountability for quality, schedule, and overall design success
- Own third-party IP integration and block-level verification through sign-off
- Mentor junior engineers to develop their technical skills and expertise
Requirements
- Bachelor's degree in Electrical Engineering or equivalent
- Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis
- Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation
- Production experience with advanced CMOS nodes (≤7nm)
- Proficiency with Cadence and/or Synopsys digital design flows
- Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
Nice to have
- Master's degree in Electrical Engineering or related field
- Hands-on collaboration with embedded firmware teams
- understanding of firmware development challenges
- Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
Skills
- Design Ownership & Execution
- Verification & Integration
- Work closely with post-silicon teams to facilitate silicon bring-up and debug
- Technical Leadership
- Actively contribute to the development and improvement of silicon development processes
- Drive design methodology improvements and CAD automation initiatives
Compensation
- Salary range is $185,000 to $230,000 depending on experience, level, and business need.
Benefits
- Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
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This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.