Architect
Member of Technical Staff - Microarchitect / RTL Design
Palo Alto · Staff+
Sponsorship not specifiedDetected 96 days ago
PythonNode.jsMachine LearningFPGAVerilogElectrical EngineeringResearchLeadershipCollaboration
About the role
- Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.
Responsibilities
- As a Founding Member of the Technical Staff on the RTL Design team at Architect, you'll own the AI-driven microarchitecture and RTL design of mission-critical SoC blocks and sub-systems (SS) going into production silicon.
- You will be expected to define, drive, and revise the block-level micro-arch specification for one of the fundamental HW accelerator blocks.
- Own AI-driven RTL design flow end-to-end (at the frontend): through code generation to incorporating feedback from lint, CDC, synthesis, and timing closure stages for closing the design loop.
- Define and maintain interface specifications (e.g. AXI, AXI-Stream, or custom-built) for block- and SS-level integration.
- Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral.
- Close collaboration with DV: Support DV bring-up with reference models, assertions, test-plans, and architectural documentation for verification closure.
- Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your own experience.
- Support FPGA prototyping on Xilinx for early functional validation.
- SystemVerilog: Clear, synthesizable, lint-clean RTL with strong design habits such as parameterization, modularity, reuse and configurability.
- Python: Strong skills for design automation, regression infrastructure, and tooling.
Requirements
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- Hands-on experience with block-specific compute datapaths and data movement
- Block-Level Depth: Hands-on experience with block-specific compute datapaths and data movement
Skills
- Degree: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- PPA Ownership: Experience taking a block from RTL through synthesis and working with PD teams on timing/area/power closure.
- FPGA prototyping experience (ideally Xilinx Vivado/Vitis).
- Competitive salary and meaningful equity stake
- Fast-paced startup with autonomy and visible impact
Compensation
- Competitive salary and meaningful equity stake
Benefits
- Experience writing SVA assertions and functional coverage for design-side verification.
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