Altera

Altera

Timing Engineer

San Jose, California, United States · Senior

Sponsorship not specified$119k-$172kDetected 30 days ago
PythonCadenceFPGAElectrical EngineeringCommunicationProblem Solving

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odds of building a lasting career here

57Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level III)83
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~45% per draw at Level III). Good if you win; have a cap-exempt backup on your list.

Lottery odds assume a STEM candidate.

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Employer immigration record

from this employer's Department of Labor filings

Green-card intent detected

Altera Corporation obtained a prevailing wage determination for Electronics Engineers, Except Computer in San Jose, CALIFORNIA on 2026-06-10. No matching green-card filing appears in our data yet. The determination expires in 2 days (2026-09-07), and a green-card filing must follow before then or the employer starts over.+2 more active determinations on file

Files H-1B transfers

13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

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About the role

  • At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
  • The ideal candidate brings strong expertise in static timing analysis (STA), timing constraints, and timing closure methodologies, with experience working on advanced process technologies.

Responsibilities

  • Drive timing closure at block level and sub-system level.
  • Developing methodology through flow/scripting which will result in easier interface timing closure at full chip.
  • Define and manage I/O timing budgets across hierarchical designs.
  • Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
  • Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
  • Work closely with design, implementation, and full chip teams to drive timing convergence, providing sign-off level expertise and guidance.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 5+ years of experience in ASIC or FPGA timing analysis and sign-off.
  • 5+ years of experience in timing analysis, static timing analysis (STA), and timing sign-off.
  • 5+ years of experience with timing constraints, STA methodologies, and timing closure at both the block and full-chip levels.
  • 5+ years of experience with synthesis, place-and-route, and parasitic extraction flows.
  • 5+ years of experience applying advanced timing concepts for leading-edge semiconductor technologies (5nm or below), including OCV, POCV, and PVT analysis.
  • 5+ years of experience performing multi-corner, multi-mode (MCMM) timing analysis.
  • 5+ years of experience using industry-standard timing analysis tools such as Cadence Tempus and Synopsys PrimeTime.
  • 5+ years of experience developing automation and scripting solutions using Tcl, Python, and/or Perl.
  • 5+ years of experience collaborating with RTL Design, Architecture, Physical Design, and Full Chip teams to drive timing closure.
  • Demonstrated ability to work independently with strong prioritization, problem-solving, and solution-oriented decision-making skills.

Nice to have

  • Experience with advanced FPGA or high-performance ASIC designs.
  • Experience defining hierarchical timing budgets and driving interface timing closure.
  • Experience generating and validating timing ECOs during implementation and sign-off.
  • Familiarity with clock tree synthesis (CTS), clock planning, and clock architecture optimization.
  • Strong understanding of digital design fundamentals and physical implementation methodologies.
  • Excellent analytical, debugging, and root cause analysis skills.
  • Shift 1 (United States of America)
  • San Jose, California, United States

Skills

  • About Altera

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $118,900 - $172,000 USD
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This listing is sourced directly from Altera's careers page and normalized into a canonical job model.