Celerocommunicationsinc
ASIC Design Engineer
Ottawa, Ontario, Canada
Sponsorship not specified$150k-$250kDetected 6 days ago
PythonVerilogElectrical EngineeringSignal ProcessingCommunicationProblem Solving
About the role
- Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will play a crucial role in designing and developing ASICs for cutting-edge technologies.
- • Design and implement digital circuits using HDL (Verilog/ System Verilog).
Responsibilities
- Design and implement digital circuits using HDL (Verilog/ System Verilog).
- Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis
- Perform RTL simulation and verification to ensure design functionality.
- Participate in design reviews and provide technical guidance to team members.
- Collaborate with cross-functional teams on system integration and validation.
- Knowledge of low-power design techniques.
- Optimize designs for performance, power, and area (PPA) requirements.
Requirements
- Bachelor's or higher degree in Electrical Engineering, Computer Engineering, or a related field.
- 3+ years of experience in digital design and verification.
- Proficiency in HDLs such as Verilog, or System Verilog.
- Strong understanding of digital design principles and methodologies.
- Familiarity with ASIC design flow, and experience with ASIC design tools.
- Experience with scripting languages (e.g., Python, Tcl).
Nice to have
- Preferred Skills
- Understanding of Optical Communication Standards is a plus.
Compensation
- $150k-$250k
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