Neurophos

Neurophos

Staff Silicon Photonics Design Engineer

San Jose, California · Staff+ · Full-time

Sponsorship not specifiedDetected 77 days ago
PythonMATLABData AnalysisANSYSCadenceElectrical EngineeringResearchPublic Speaking

About the role

  • We are seeking an experienced Silicon Photonics Designer to join our SiPh team.

Responsibilities

  • Develop waveguide routing, splitters, polarization splitters/rotators (PSR), crossings, and other PIC sub-elements with explicit attention to insertion loss, return loss, bandwidth, polarization dependence, and process variation tolerance.
  • perform tolerance and process-corner analysis to ensure robust yield across foundry runs.
  • Implement PIC layouts using Cadence Virtuoso, KLayout, or script-based parametric design flow, generate DRC-clean GDS for submission to foundry, including DRC/LVS sign-off, design review, and mask data preparation.
  • Manage and drive tapeout processes with mainstream SiPh foundries, or equivalent silicon photonics PDKs
  • Interface directly with foundry process engineers to negotiate design rule waivers, understand process corners, and resolve integration challenges throughout the design cycle.
  • Define and execute design-of-experiments (DOE) test chip strategies to characterize process sensitivities and close the loop between simulation and measurement results.
  • Conduct FDTD, eigenmode expansion (EME), and circuit-level simulations using Ansys Lumerical, Synopsys Optsim, or equivalent tools; perform tolerance and process-corner analysis to ensure robust yield across foundry runs.
  • Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light.
  • This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

Requirements

  • Proficiency with photonic simulation tools: FDTD, BPM, FDE, CMT, and EME solvers (Ansys Lumerical Suite, Synopsys Rsoft, Photon Design, or equivalent) and circuit-level simulation.
  • Demonstrated PIC layout experience using Cadence Virtuoso, KLayout, and/or Python-based parametric layout frameworks (GDSFactory, IPKISS, or similar) for GDS generation.
  • Experience with at least one commercial silicon photonics foundry PDK and tapeout flow (TSMC, GlobalFoundries - GF Fotonix /AMF, Tower, AIM Photonics, or equivalent).
  • Direct foundry interface experience with silicon photonics platforms-including DRC/LVS sign-off, OPC coordination, and MPW/dedicated wafer shuttle management.
  • M.S. or Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline
  • 3+ years of hands-on silicon photonics design experience in an industry setting (or equivalent depth of graduate research with demonstrated tapeout and measurement record).
  • Proven expertise in designing passive silicon photonic components: edge couplers, grating couplers, directional/hybrid couplers, waveguides, and splitters on SOI platforms.
  • Familiarity with electro-optic device design (Lasers, MZM, ring modulator, Ge photodetector) to enable holistic PIC integration.
  • Experience with coherent PIC design elements: IQ modulators, optical hybrids (90° hybrid), polarization splitters/rotators, and balanced detector integration.
  • Full tape-out ownership: concept → simulation → layout → DRC clean → tapeout → wafer receipt → measurement → design iteration.
  • Strong knowledge on high-speed optoelectronics device design and measurement

Skills

  • Programming proficiency in Python and/or MATLAB for simulation automation, data analysis, and statistical evaluation of device performance.
  • Working knowledge of datacom or coherent transceiver link architectures and system-level optical specifications.
  • Familiarity with SiN photonics platforms (low-loss, broadband) for edge coupler or wavelength-routing applications.
  • coupling loss/insertion loss characterization, swept-wavelength spectral measurements, polarization-dependent loss (PDL) measurements.
  • Exposure to co-packaged optics (CPO) architectures, flip-chip or die bonding of III-V laser sources, or heterogeneous photonic integration.
  • Experience with automated measurement scripting (Python GPIB/VISA frameworks, automated wafer-level or die-level test stations).
  • Come help us bring this transformative technology to the world.
  • Unlimited PTO. No rigid vacation banks, just a focus on delivery.
  • 401(k) matching and stock option opportunities to ensure our success is your success.
  • Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
  • Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don't.

Benefits

  • 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
  • Unlimited PTO.
  • No rigid vacation banks, just a focus on delivery.
  • Personalized Benefits.

Company info

  • We've assembled a world-class team of industry veterans and recently raised a $110M Series A https://www.neurophos.com/110m-raise led by Gates Frontier.
  • Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team.
  • At Neurophos, we offer:

Visa & Work Authorization

  • Experience with automated measurement scripting (Python GPIB/VISA frameworks, automated wafer-level or die-level test stations).
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