Astera Labs Inc.
Principal Advanced Packaging Engineer
San Jose, California, United States · Principal
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$13,899 more — $218,899 — moves this role to Level IV and 4 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $218,899 would place this position at wage Level IV. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- This is a senior individual contributor role focused on setting technical direction and driving packaging technology development for NPO and CPO products.
Responsibilities
- Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
- Define and optimize wafer-level, panel-level, or die-level packaging process flows.
- Drive EIC-to-PIC integration and broader optical device integration efforts.
- Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.
- Develop and maintain packaging PDKs and design rules for NPO and CPO products.
Requirements
- 8+ years of experience in semiconductor or advanced packaging engineering, with demonstrated technical leadership.
- Experience with silicon photonics chip packaging and EIC/PIC integration.
- Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.
- Proven track record of equipment and process qualification with OSAT or tool suppliers.
- Experience with PDK development and packaging design rule authoring.
Nice to have
- Hands-on experience with CPO or NPO product development.
- Experience with optical coupling or waveguide alignment for photonic integration.
- Familiarity with DFM and DFT for advanced packaging.
Skills
- Labs (NASDAQ:
- ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Discover more at www.asteralabs.com.
- Principal Advanced Packaging Engineer:
Compensation
- Salary range is $205,000 to $260,000 depending on experience, level, and business need.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.