Ciena
Senior Physical Design Engineer
Ottawa · Senior
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About the role
- We're a technology company shaping the future of networking, guided by innovation, integrity, and collaboration.
- Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
- We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
Responsibilities
- Scope and define the physical architecture of designs, utilizing EDA vendor tools to build, adapt, and maintain a robust flow from netlist to full closure and GDSII generation.
- Partner with RTL circuit designers and other layout engineers to create optimal floorplans, design power grids, and clock distribution networks that achieve the best performance and power efficiency.
- Collaborate with analog designers and ASIC/SoC teams to integrate analog blocks seamlessly into the overall design.
- Conduct initial Place & Route trials to refine design and correlation, influencing circuit architecture by working closely with RTL designers and architects to ensure reliable and closable physical design.
- Generate and implement timing ECOs to achieve timing closure, as well as functional ECOs to address RTL feature fixes when necessary.
- Utilize tools like Formality or Conformal for formal verification, analyzing reports and ensuring design accuracy and integrity.
- Write scripts to enhance productivity and efficiency for yourself and other backend engineers. Collaborate with tool and technology vendors to drive fixes, improve workflows, and evaluate new tools and features.
- Your expertise in physical design, collaboration with cross-functional teams, and ability to innovate will be instrumental in advancing Ciena's cutting-edge optical networking solutions.
- Practical experience developing scripts to automate tasks throughout the backend flow.
- At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.
Requirements
- Minimum Bachelor's degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with significant experience in ASIC physical digital design and timing closure
- Experience with physical verification (Calibre).
- Experience with power integrity (EMIR)
- Experience with Static Timing Analysis (STA)
- Experience with physical synthesis and full RTL-to-GDS flow using industry-standard EDA tools
Compensation
- The salary range for this role in Ottawa is $109, 000 - $174, 000
- Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business.
- Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
- Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission.
- In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time.
Equal opportunity
- If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
- Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
This listing is sourced directly from Ciena's careers page and normalized into a canonical job model.