Astera Labs Inc.

Technical Lead Design Verification Engineer

San Jose, CA

Work authorization required$147k-$195kDetected 5 days ago

PythonC++ExpressComplianceVerilogControlsCommunicationProblem Solving

About the role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage.

≥5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications.
Knowledge of industry-standard simulators, revision control systems, and regression systems.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision.
Required Experience
Experience with full verification lifecycle based on System Verilog/UVM/C/C++.
Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures.
Working experience with scripting tools (Perl/Python) to automate verification infrastructure.
Experience with directed test based methodologies, cache verification and formal methods.

ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
Discover more at www.asteralabs.com.
Experience with System Verilog, C, C++, Python or other scripting languages would be a plus.
You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms.
Strong academic and technical background in electrical engineering.
At minimum, a Bachelor's in EE is required, and a Masters is preferred.
Experience in formal methods is a plus.
Preferred Experience

This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.