credosemi

credosemi

Director, ASIC Design

San Jose, California · Director

Sponsorship not specified$210k-$240kDetected 11 days ago
PythonCadenceVerilogElectrical EngineeringLeadershipCommunicationCollaboration

About the role

  • In this role, you will be responsible for driving chip development from concept to production, managing high-performing teams, and ensuring successful execution of complex ASIC projects.

Responsibilities

  • Lead chip development: Oversee design, verification, validation, and physical implementation of complex ASIC projects to ensure bug-free, high-quality silicon.
  • Manage design & verification teams for large, high-speed ASICs.
  • Project planning & execution: Develop and maintain project schedules, ensuring timely delivery.
  • Provide technical leadership through all phases of ASIC development: architecture, micro-architecture, RTL design, verification, timing closure, and physical design.
  • Collaborate with PD, DFT, STA, PV, and system teams for successful tape-outs and chip bring-up.
  • Oversee design, verification, validation, and physical implementation of complex ASIC projects to ensure bug-free, high-quality silicon.
  • Develop and maintain project schedules, ensuring timely delivery.
  • architecture, micro-architecture, RTL design, verification, timing closure, and physical design.
  • As a Director, ASIC Design you will lead the development of advanced ASIC solutions for next-generation data communication products.
  • You will provide technical leadership, collaborate across functions, and deliver high-quality silicon that meets stringent performance and reliability standards.

Requirements

  • MS degree in Electrical Engineering or Computer Science with 15+ years of relevant experience in ASIC design.
  • Proficiency in Verilog/SystemVerilog RTL design.
  • Knowledge of synthesis and static timing analysis.
  • familiarity with UVM.
  • Hands-on experience with chip bring-up and validation.
  • Proven track record of successful production tape-outs.
  • Hands-on experience with STA and timing closure.

Nice to have

  • Expertise in scripting languages (Python, Tcl, Perl, Shell).
  • Knowledge of EDA tools (Synopsys, Cadence, Mentor).
  • Experience with high-speed interfaces or SerDes.
  • Credo is an Equal Opportunity Employer.

Skills

  • Credo is engineering the future of high-speed connectivity for the AI-driven world.

Compensation

  • The base salary range for this position is $210,000 – $240,000 a year.

This listing is sourced directly from credosemi's careers page and normalized into a canonical job model.