Nuvacore
CPU Verification Engineer
Austin, TX · Senior · Full-time
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$12,360 more — $152,360 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $152,360 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · Austin-Round Rock-San Marcos, TX. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Generate complex directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
- Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
- Test & Debug: Generate complex directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
Responsibilities
- Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads.
- Drive the verification scope, strategy, and test plans for the CPU at unit and/or top level of the CPU design.
- Partner with architects to correlate RTL against performance models, hunting throughput, stall, and branch-prediction-accuracy issues.
- Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.
- Plan & Strategy: Drive the verification scope, strategy, and test plans for the CPU at unit and/or top level of the CPU design.
- Performance Verification: Partner with architects to correlate RTL against performance models, hunting throughput, stall, and branch-prediction-accuracy issues.
- Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.
Requirements
- Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
- Strong knowledge of CPU micro-architecture and digital logic - pipelines, out-of-order execution, and branch prediction.
Nice to have
- Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python
Compensation
- $140k-$250k
Benefits
- Build, maintain, and scale robust verification environments - stimulus generators, checkers, transactors, and coverage - that exercise the pipeline end to end.
Company info
- We are seeking Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove the correctness of the Nuvacore CPU.
- As part of the design verification (DV) team, you will help verify by building the test plans, environments, and checkers that find deep bugs in the pipeline long before silicon, working shoulder-to-shoulder with architecture and RTL design.
This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.