Astera Labs Inc.
Senior Manager, Digital Design
San Jose, California, United States · Senior
Sponsorship not specified$216k-$240kDetected 4 days ago
Electrical EngineeringLeadership
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odds of building a lasting career here
64Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
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Files H-1B transfers
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About the role
- As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives.
- This is an opportunity to influence the development of purpose-built connectivity products at a hyper-growth company, establish scalable design practices, and help deliver silicon that advances the next generation of AI systems.
Responsibilities
- Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment.
- Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.
- Partner with architecture and system teams to translate PCIe & CXL, UAL, ethernet requirements into robust, scalable digital implementations.
- Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle.
- Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams.
- Lead, mentor, and develop a team of 6-8 digital design engineers, fostering technical excellence, accountability, and effective collaboration.
- As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure.
- You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.
- 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design.
Nice to have
- Track record of balancing performance, power, area, schedule, and risk across large SoC or ASIC programs.
- Master's or PhD in Electrical Engineering, Computer Engineering, or a related field.
Skills
- End-to-End Chip Development
- RTL Quality and Tape-Out Readiness
- Team and Cross-Functional Leadership
- Influence cross-functional development decisions and align engineering teams around quality, risk reduction, and on-time execution.
- Communicate technical status, tradeoffs, dependencies, and mitigation plans to engineering and program leadership.
Compensation
- Salary range is $216,000 to $240,000 depending on experience, level, and business need.
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This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.