Silicon Labs
Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin · Staff+
Sponsorship not specified$10k-$20kDetected 30 days ago
PythonGitMachine LearningVerilogElectrical EngineeringCommunication
About the role
- Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant's skill set.
- Silicon Labs is an equal opportunity employer and values the diversity of our employees.
Responsibilities
- Develop complex SOC/chip Architectures with multiple processors, digital and mixed signal subsystems, multiple power, and clock domains with a goal towards optimizing power for specific customer scenarios.
- Define and implement SoC-level low-power architecture, including power domains, retention, isolation, level shifters, and power sequencing.
- Develop and integrate UPF/CPF-based power intent across subsystem and SoC hierarchies.
- Collaborate with architects to define power management strategies that meet performance, power, and area targets.
- Design and integrate clocking infrastructure, including clock generation, clock distribution, clock gating, clock muxing, reset architectures, and clock monitoring mechanisms.
- Drive RTL design and integration of power management controllers, clock controllers, reset controllers, and related infrastructure IPs.
- Prepare and hold architecture, design, and verification reviews with technical staff throughout project lifecycle
- Lead small teams of design engineers to architect, design and verify digital subsystems.
- Drive subsystem and SoC integration activities, ensuring seamless connectivity between processors, memories, peripherals, accelerators, and third-party IPs.
- Drive RTL development and integration of infrastructure IPs, including clock controllers, reset controllers, power management controllers, DMA engines, and bus fabric components.
Requirements
- Extensive experience with low-power design methodologies, including UPF, power gating, retention, isolation, level shifting, and power-aware verification.
- Strong experience with industry-standard on-chip bus protocols such as AXI, AHB, APB, and related interconnect architectures.
- Experience integrating complex subsystems, processor clusters, memory subsystems, and third-party IPs into large SoCs.
- Knowledge of embedded processor systems and C coding
- Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools
- Experience with logic synthesis and timing constraints
- Experience with scripting and automation.
- Knowledge of Python, Perl, and Tcl
- Experience with revision control and configuration management systems (such as Perforce, Git, Methodics)
- Demonstrated ability to generate high output in a self-driven manner
Compensation
- Highly competitive salary
- 3 paid volunteer days per year
- The annualized base pay range for this role is expected to be between $143,150 - $265,850 USD.
Benefits
- Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans
- Equity rewards (RSUs)
- Life/AD&D and disability coverage
- Flexible spending accounts
- Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
- Flexible PTO schedule
- Tuition reimbursement
- Monthly wellness offerings
- Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.
- You can look forward to the following benefits:
Company info
- We strive to provide advanced technology solutions through innovation in custom RISC-V Cores and AI/ML components.
Equal opportunity
- equal opportunity employer and values the diversity of our employees.
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