Bolt Graphics

Bolt Graphics

Lead Hardware System Architect

Sunnyvale, CA

Sponsorship not specified$200k-$250kDetected 20 days ago
PCB DesignCadenceElectrical EngineeringHardware DesignAdaptability

About the role

  • In this role, you will not just oversee board layouts; you will define the physical topologies that enable cutting-edge graphics compute scaling.
  • Management Integration: Ensure seamless integration of out-of-band telemetry and management infrastructure, designing physical routing for Baseboard Management Controllers (BMCs), SPI, and I2C/SMBus topologies.

Responsibilities

  • Physical System Architecture & High-Performance Graphics Design Architect the Platform: Drive system-level architectural trade-offs, balancing high-performance GPU silicon package constraints, high-speed routing density, thermal mechanics, and ultra-high-density power delivery networks (PDNs).
  • Own High-Speed Topologies: Design and optimize complex PCB topologies utilizing PCIe Gen 5/Gen 6 (CEM specifications) and proprietary/consortium scale-up interconnect fabrics designed for parallel compute and graphics scaling (e.g., NVLink, Infinity Fabric, UA Link).
  • Systemic Co-Design: Collaborate with Silicon, Signal/Power Integrity (SI/PI), and Thermal/Mechanical teams to define robust board stack-ups, low-loss material selection, and multi-phase power zones handling massive transient loads from modern graphics processors.
  • Technical JDM/ODM & Supplier Governance Lead Technical Enablement: Serve as the primary technical authority interfacing with international JDM/ODM layout and hardware engineering teams.
  • Triage & Failure Analysis: Lead complex hardware debug, component-level troubleshooting, and failure analysis (FA) during early-phase platform bring-up and validation of graphics compute hardware.
  • DFX & Execution Governance: Enforce rigorous design reviews and strict compliance with DFX (Manufacturing, Assembly, Test, and Automation) standards to ensure high-yield transitions from EVT/DVT to High-Volume Manufacturing (HVM).
  • Selflessly collaborate towards our shared purpose.
  • Drive system-level architectural trade-offs, balancing high-performance GPU silicon package constraints, high-speed routing density, thermal mechanics, and ultra-high-density power delivery networks (PDNs).
  • Design and optimize complex PCB topologies utilizing PCIe Gen 5/Gen 6 (CEM specifications) and proprietary/consortium scale-up interconnect fabrics designed for parallel compute and graphics scaling (e.g., NVLink, Infinity Fabric, UA Link).
  • Collaborate with Silicon, Signal/Power Integrity (SI/PI), and Thermal/Mechanical teams to define robust board stack-ups, low-loss material selection, and multi-phase power zones handling massive transient loads from modern graphics processors.

Requirements

  • Fabric & Bus Expertise: Deep, hands-on experience designing with PCIe Gen 5/6 and high-speed serdes (112G/224G PAM4 architectures).
  • Familiarity with CXL or scalable interconnect fabrics is highly desired.
  • Advanced Power & SI/PI: Strong understanding of high-frequency PCB layout constraints, via optimization, and power delivery networks capable of handling extreme di/dt step loads inherent to dynamic graphics workloads.
  • Hardware Tooling: Proficiency with advanced EDA tools (e.g., Cadence Allegro, OrCAD) and familiarity with simulation tools for validating physical design assumptions.
  • Global Vendor Triage: Experience directing overseas ODM engineering teams through architectural definition, layout execution, and laboratory hardware triage.
  • Proficiency with advanced EDA tools (e.g., Cadence Allegro, OrCAD) and familiarity with simulation tools for validating physical design assumptions.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.

Nice to have

  • Direct experience with Open Compute Project (OCP) standards or industry-standard multi-GPU form factors.
  • Hands-on lab experience utilizing high-speed validation equipment (e.g., oscilloscopes, VNAs, BERTs) for signal and power verification on graphics hardware.
  • Experience directing overseas ODM engineering teams through architectural definition, layout execution, and laboratory hardware triage.

Compensation

  • $200,000-$250,000 per year (California).
  • This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.
  • This role is onsite - 5 days a week.

Company info

  • Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors.
  • We pride ourselves on our first principles approach to solving problems.
  • We are energized by our mission to reduce the barrier of entry for content creation and consumption.
  • Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.
  • Unmute yourself.
  • Test boundaries and get proven right.
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This listing is sourced directly from Bolt Graphics's careers page and normalized into a canonical job model.