Lattice Semiconductor
Product Test Engineer
Hillsboro, OR
Sponsorship not specifiedDetected 21 days ago
PythonC++LinuxCustomer SuccessCustomer SupportFPGAVHDLVerilogProblem SolvingMicrosoft Office
About the role
- Lattice Overview There is energy here…energy you can feel crackling at any of our international locations.
- Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.
Responsibilities
- Develop test plans using established methodologies targeted on chip IP functions and features.
- Design and implement test circuits using FPGA fabric and embedded IP using Lattice's proprietary design SW.
- Develop scripts to automate test generation and own Pre-Si verification of content to ensure Si readiness.
- Identify and analyze to root cause product marginalities, communicating and coordinating root cause closure to appropriate cross-functional team (eg. Applications Engineering, Design Engineering, etc.)
- Take ownership of IP content development and drive any issues to resolution.
Requirements
- BS degree (Electrical, Electronics or Computer Engineering) with 8 years of industry experience, or
- MS degree (Electrical, Electronics or Computer Engineering) with 6 years of industry experience
- Good working knowledge of semiconductor devices and test methodologies
- Experience in IC characterization and/or failure analysis using various bench tools (i.e. Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, etc)
- Experience with WAT/etest, wafer sort, package assembly, final test (i.e. full backend IC process)
- Experience in Programmable Logic is desired
- Knowledge in test, DFT methodologies (ie. scan, BIST), memory test, and fault grade methodologies an advantage
- Knowledge in Hardware Description Language such as Verilog or VHDL an advantage
- Knowledge in programming languages (ie.
- Demonstrated ability to work with multiple groups and across cultures
Nice to have
- Experience in ATE test program development, integration and debug on Nextest Magnum, Advantest T2K or Teradyne UltraFLEX preferred.
Skills
- Python, C++) • Excellent verbal and written skills.
Compensation
- In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Benefits
- Extract coverage metrics of test patterns using fault grading and review for coverage improvements.
Company info
- For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com.
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