Altera
Memory Validation Architect
San Jose, California, United States · Senior
Sponsorship not specified$210k-$303kDetected 24 days ago
PythonC++CExpressAlgorithmsFPGAElectrical EngineeringLoad TestingTest AutomationLeadershipCommunicationMentoring
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odds of building a lasting career here
61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
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from this employer's Department of Labor filings
Green-card intent detected
Altera Corporation obtained a prevailing wage determination for Electronics Engineers, Except Computer in San Jose, CALIFORNIA on 2026-06-10. No matching green-card filing appears in our data yet. The determination expires in 2 days (2026-09-07), and a green-card filing must follow before then or the employer starts over.+2 more active determinations on file
Files H-1B transfers
13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.
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About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- This is a highly visible technical leadership role responsible for shaping the validation strategy for DDR5, LPDDR5/LPDDR6, HBM, and future memory technologies from architecture definition through production.
- The ideal candidate is a recognized industry expert with deep experience in memory controller and PHY architectures, post-silicon validation, system architecture, silicon debug, and customer enablement.
Responsibilities
- Define and own the end-to-end validation architecture and strategy for memory subsystems across multiple FPGA product families.
- Drive validation planning from architecture definition through silicon bring-up, product qualification, and customer deployment.
- Lead pre-silicon and post-silicon validation strategy for:
Requirements
- OR Master's degree with 13+ years of related industry experience
- OR Ph.D. with 10+ years of related industry experience.
- 10+ years of hands-on experience designing, validating, debugging, or optimizing DDR memory technologies, including DDR4, DDR5, LPDDR4, LPDDR5, HBM, or newer JEDEC-compliant memory standards.
- 8+ years of experience leading or contributing to silicon bring-up, silicon debug, characterization, validation, and production qualification for complex SoCs or memory subsystems.
- 8+ years of experience performing board-level signal integrity (SI), power integrity (PI), timing analysis, or high-speed memory channel validation.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 15+ years of industry experience in memory subsystem architecture, silicon validation, high-speed interface development, or a related field; OR Master's degree with 13+ years of related industry experience; OR Ph.D. with 10+ years of related industry experience.
- 10+ years of experience with at least four of the following: Memory controller architecture or DDR PHY architecture or Memory initialization and training or DDR calibration algorithms or JEDEC memory specifications or Memory timing analysis and scheduling
- 5+ years of hands-on experience using high-speed laboratory validation equipment such as oscilloscopes, protocol analyzers, logic analyzers, Bit Error Rate Testers (BERTs), traffic generators, or equivalent debugging tools.
- 5+ years of programming or automation experience using Python, C/C++, or similar scripting or programming languages to develop validation, debug, characterization, or test automation solutions.
- 5+ years of experience leading cross-functional technical projects involving at least three of the following disciplines: architecture, RTL design, firmware, silicon validation, software development, customer engineering, or product engineering.
Nice to have
- Experience with FPGA or ASIC memory subsystem development.
- Expertise in HBM, CXL Memory, Compute Express Link, or emerging memory technologies.
- Experience working with major DRAM vendors including Micron, Samsung, and SK hynix.
- Strong understanding of PCIe, CXL, AXI, AMBA, and coherent interconnect architectures.
- Experience defining organization-wide validation methodologies and automation frameworks.
- Demonstrated success influencing architecture decisions across multiple product generations.
- Experience leading globally distributed engineering teams and mentoring senior technical contributors.
- Shift 1 (United States of America)
Skills
- About Altera
- Architect scalable validation frameworks, reusable infrastructure, and automation capable of supporting multiple product generations.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $209,500 - $303,000 USD
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.