Astera Labs Inc.
Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet
San Jose, California, United States · Principal
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$2,408 more — $187,408 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $187,408 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- We are seeking an experienced Principal / Senior Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure. This is a highly visible technical leadership role where you will define verification strategies, drive methodology improvements, mentor engineering teams, and collaborate across architecture, RTL, firmware, validation, and silicon teams to ensure first-pass silicon success.
- The ideal candidate is passionate about building world-class verification environments, has deep expertise in protocol verification, and enjoys solving complex architectural challenges.
- We are seeking an experienced Principal / Senior Principal Design Verification Engineer to lead the verification of next-generation connectivity IPs and SoCs powering AI and cloud infrastructure.
Responsibilities
- Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.
- Identify verification risks early and proactively drive mitigation plans.
- Lead technical reviews including architecture, RTL, verification, and tape-out readiness reviews.
- Design Verification
- Architect and develop scalable UVM/System Verilog verification environments.
- Drive regression planning, automation, and continuous integration improvements.
- Develop reusable VIP and verification infrastructure across multiple product lines.
- Lead verification efforts involving one or more of:
- Work closely with Architecture teams to influence design for verification.
- Partner with RTL designers during implementation and debug.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- Strong expertise in System Verilog and UVM.
- Extensive experience in verification planning, execution, and sign-off.
- Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
- Strong experience in several of the following areas:
Nice to have
- Define verification methodologies, reusable verification frameworks, and best practices across multiple programs.
- Debug complex RTL, protocol, timing, and integration issues.
- Compute Express Link (CXL 2.x / 3.x)
- PCI Express (Gen4/Gen5/Gen6)
- Ethernet (10G-800G)
- High-speed SerDes interfaces
- Memory interfaces including DDR/LPDDR/HBM (preferred)
- Support customer issue analysis and silicon bring-up when required.
Compensation
- Salary range will be is $185,000 to $230,000 depending on experience, level, and business need.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.