Etched
DFT Intern
San Jose · Intern · Internship
Sponsorship not specifiedDetected 99 days ago
PythonSpringNLPVerilogElectrical EngineeringResearchMentoring
About the role
- You do not necessarily need prior DFT experience
- just the ability to learn quickly in a fast-paced, high-autonomy environment.
- We are looking for Summer '26, Fall '26, Spring '27, and Summer '27 interns.
Responsibilities
- As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius.
- You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models.
- Exposure to ASIC or SoC design concepts
- Generous housing support for those relocating
Requirements
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with a hardware description language (Verilog or SystemVerilog)
- Familiarity with scripting in Python, Tcl, or another language
- Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
- Experience with Tessent or similar DFT tooling
- Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
- Familiarity with clocking and reset schemes
This listing is sourced directly from Etched's careers page and normalized into a canonical job model.