Netpreme

Member of Technical Staff, ASIC Design

Santa Clara, CA · Staff+

Sponsorship not specifiedDetected 217 days ago

LLMsStakeholder ManagementVerilogElectrical EngineeringLeadershipCommunicationCollaboration

About the role

We are seeking experienced Senior ASIC Designers.
You will be part of an early-stage startup working on an exciting product in the Artificial Intelligence/DataCenter space.
This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.

You'll work from first principles, move quickly from insight to execution, and see your contributions directly reflected in what we build.
This role demands proven technical expertise in advanced ASIC design flows, and leadership in execution, cross-functional coordination, and final product delivery.
Provide technical leadership in defining IP/SOC microarchitecture specifications, and design methodologies. Conduct design reviews to ensure adherence to best practices.
Guide the team in optimizing the design to meet aggressive performance, power and area goals using advanced architectural and design techniques.
Drive effective and seamless collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality.
Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in a timely fashion to support team deliverables.

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Proficiency with front-end development tools/methodologies, and scripting for automation and flow integration.
Minimum of 5+ years of ASIC/SOC digital design experience
Excellent leadership, communication, team building and stakeholder management skills.
Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.
Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
Design and tapeout of any advanced silicon device is highly preferred.

PhD in Electrical Engineering, Computer Engineering, or a related field.
Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
Relocation assistance and visa sponsorship
The work we do here compounds across state-of-the-art AI models, systems, and real-world applications.
Timing: Joining now means real ownership of the company and meaningful influence over product direction and execution.
Culture: You'll work alongside a group of people who care deeply about rigor, clarity, and impact.
This is a place where strong ideas shine, curiosity is encouraged, and growth is a daily practice.

Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.

Competitive salary commensurate with experience including base salary, performance-based bonus, and early stage equity grant
Well-equipped, sunny offices in Santa Clara, CA and Boston, MA
Relocation assistance and visa sponsorship

The work involves learning advanced LLM in modern data centers and applications to design memory acceleration.
Comprehensive benefits including health, dental, vision, and life insurance
Perks include a daily lunch stipend, 401k match, and more
A collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing

We are tackling a fundamental challenge at the infrastructure layer: unlocking greater AI capability while dramatically improving efficiency.
You'll work alongside a group of people who care deeply about rigor, clarity, and impact.
We value thoughtful disagreement, fast learning, and intellectual fearlessness.
Impact: We are tackling a fundamental challenge at the infrastructure layer: unlocking greater AI capability while dramatically improving efficiency.
As part of the Silicon Design Team, responsible for RTL design of IPs, subsystems and SOCs supporting Netpreme's silicon roadmap.

This listing is sourced directly from Netpreme's careers page and normalized into a canonical job model.