Astera Labs Inc.
Principal Engineer - Validation Engineering
San Jose, California, United States · Principal
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
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Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
The bottom of this range ($185,000) is below the Level I prevailing wage of $186,264. An H-1B cannot be filed below the prevailing wage, so an offer at the floor of this band could not be sponsored as posted.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $219,315 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Architectural and Engineering Managers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Architectural and Engineering Managers (11-9041) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- This role combines deep hands-on technical leadership with broad cross-functional influence.
Responsibilities
- Lead silicon, board, and system bring-up, including test environment definition, instrumentation selection, configuration, and execution.
- Develop, review, and maintain Python-based automation and data analysis tools in Linux-based validation environments.
- Drive root-cause analysis of functional, performance, interoperability, reliability, and system-level issues across hardware, firmware, and software boundaries.
- Partner with design, firmware, software, product, applications, and customer teams to resolve issues and deliver high-quality releases.
- Mentor engineers, establish validation best practices, and represent validation status and technical recommendations in design and launch reviews.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 8-12 years of experience in hardware, silicon, system, or product validation engineering.
- Proven experience leading validation for semiconductor, networking, connectivity, or data center products.
- Excellent written and verbal communication skills, with the ability to influence technical decisions across functions.
Nice to have
- Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience validating high-speed connectivity interfaces such as PCIe, CXL, Ethernet, or comparable technologies.
- Understanding of physical-layer fundamentals, signal integrity, protocol analysis, compliance, and interoperability testing.
- Proficiency with Python, Linux, laboratory equipment, data analysis, and Microsoft Azure DevOps or comparable validation infrastructure.
- Experience scaling validation labs, working with hyperscalers or ODMs, and mentoring engineers in a fast-paced, high-growth environment.
Compensation
- Salary range is $185,000 to $240,000 depending on experience, level, and business need.
Benefits
- Define validation methodologies, coverage goals, schedules, dependencies, and exit criteria for complex hardware and connectivity products.
- Architect scalable lab infrastructure and automated test frameworks that improve coverage, repeatability, debug efficiency, and time to qualification.
Company info
- Your work will directly support Astera Labs' hyper-growth mission to enable purpose-built, rack-scale AI connectivity and help customers deploy high-performance systems with confidence.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.