Asteraearlycareer2026
Design Verification Engineer (Intern 2026)
Toronto, Ontario, Canada · Intern · Internship
Work authorization requiredDetected 5 days ago
PythonVerilogCommunication
About the role
- .Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- The ideal candidate will be passionate about silicon engineering with a background in VLSI and/or computer architecture.
Requirements
- Required experience:
- Familiarity with any of the scripting languages Python, Perl, etc. and hands-on experience in C/C++.
Nice to have
- Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.
- Knowledge of communication interfaces like SPI, I2C, JTAG.
- Courses in digital communications and computer networks.
- System Verilog test bench(UVM)
- Familiarity with Synopsys EDA tools.
- Preferred experience:
Skills
- ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Discover more at www.asteralabs.com.
Visa & Work Authorization
- Authorized to work in Canada and start immediately.
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