Altera
Functional Safety Architect
San Jose, California, United States · Senior
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$5,382 more — $154,482 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $154,482 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Computer Occupations, All Other" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Computer Occupations, All Other (15-1299) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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from this employer's Department of Labor filings
Green-card intent detected
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- Become a member of our world-class SoC architecture and development team!
- Define safety architecture techniques (lockstep CPUs, ECC memories, watchdogs, redundancy).
Responsibilities
- Collaborate with the Architects, Silicon Design, Software teams to architect new safety concepts and safety mechanism features and guide future development.
- Perform safety analyses (FTA, FMEA, DFA methodologies) against CCF, CF to ensure FFI, independence & Fault tolerance requirements are met.
- Review hardware/software safety designs for compliance and feasibility.
- Collaborate with design verification teams to define safety V&V strategy (fault injection, fault simulation, test methodologies).
- Document and present defensible safety case evidences aligned with IEC 61508, ISO 26262 ensuring clarity and traceability for stakeholders and assessors.
- Support process related activities in achieving systematic capability (SIL3/ASIL D)
- Excellent written & oral communication skills to construct clear, evidence-based safety arguments and build trust in safety cases with both internal and external stakeholders
Requirements
- Bachelor's or Master's degree in Electrical Engineering or related field + 10 years silicon industry experience or MS + 8 years of silicon industry experience
- 7+ years of safety professional experience, including possessing certifications (Eg.
- 7+ years of experience in certifying devices from concept through certification for ASICs/PLDs/CPUs with EXIDA, TUeV or Equivalent
- 7+ years of experience with SysML, FMEA/FMEDA, FTA, HAZOP and requirements-management tooling (e.g., Jama).
- Applicants must be eligible for any required U.S. export authorizations.
- 7+ years of safety professional experience, including possessing certifications (Eg. FSCP, FS Professional license)
Nice to have
- Familiarity with RTL coding and simulations/debug of SoC Architectures.
- Desire to commit and follow through on complex, multi-year programs
- Ability to resolve complex issues in creative, efficient, and effective ways
- Hands-on experience with creating safety documents (Safety Cases, Safety Management Plans, Safety Manuals) is a plus.
- Functional Safety Management (safety manager) experience in achieving systematic capability SC3/ASIL D is a plus.
- US Citizenship is a plus.
- Shift 1 (United States of America)
- San Jose, California, United States
Skills
- Demonstrated strong ability to move seamlessly between levels of abstraction - from system to the "nuts and bolts" implementation
- About Altera
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $149,100 - $215,000 USD
Benefits
- Guide teams on ASIL/SIL decomposition, fault tolerance, diagnostics coverage, etc.
- Ensure achievement of diagnostic coverage metrics (SPFM, LFM, PMHF).
Visa & Work Authorization
- US Citizenship is a plus
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.