Astera Labs Inc.
Manager, ATE Test Engineering
San Jose, California, United States · Senior
Sponsorship not specified$195k-$250kDetected 7 days ago
PythonC++CProduct ManagementElectrical EngineeringHardware DesignLeadership
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odds of building a lasting career here
64Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
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About the role
- This is a critical leadership role responsible for driving next-generation high-speed, high-performance products from silicon bring-up through high-volume manufacturing in advanced process nodes.
- This is an opportunity to combine technical depth with engineering leadership at a hyper-growth connectivity company.
- Your decisions will directly influence product quality, manufacturing readiness, and customer experience.
Responsibilities
- Build, mentor, and lead a high-performing team of ATE Test engineers owning a diverse portfolio of connectivity products purpose-built for AI infrastructure
- Define end-to-end ATE test strategies and plans for high-speed connectivity products from design engagement through high-volume production.
- Lead silicon and ATE bring-up, bench-to-ATE correlation, production release, and ongoing test optimization.
- Drive characterization and production test of high-speed SerDes and mixed-signal interfaces, including PCIe, Ethernet, DDR, NVMe, and USB.
Requirements
- Bachelor's degree in electrical engineering or related technical field.
- 8+ years of experience developing and supporting ATE test solutions for complex High-speed products or SoC products.
- Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB.
- Experience with ATE program development, silicon bring-up, bench-to-ATE correlation, production debug, and test-time optimization.
Nice to have
- Master's or PhD in Electrical Engineering or related field.
- Strong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, plus control interfaces including I2C, I3C, SPI, MDIO, and JTAG.
- Experience testing high-speed SerDes operating at 16 Gbps or higher, including external loopback at wafer sort.
- Proficiency in C/C++ or Python for ATE programming, data processing, and automation
- familiarity with modern databases and RF testing on ATE platforms.
Skills
- Team Leadership & Organization Building
- Establish scalable processes, best-known methods (BKMs), and operational excellence frameworks as the organization grows
- Make sound technical and organizational decisions in a fast-paced, dynamic environment with competing priorities
- Test Strategy and Product Ownership
- ATE Hardware, Software, and Silicon Validation
- Guide to tester platform selection and development of load boards, interface hardware, and test solutions for wafer sort and final test.
- Direct ATE program development, pattern implementation, debug, and resource optimization on Advantest 93k or Teradyne platforms.
- Cross-Functional Leadership and Manufacturing Execution
Compensation
- Salary range is $195,000 to $250,000 depending on experience, level, and business need.
Benefits
- Establish coverage, quality, test-time, cost, and yield objectives, and drive measurable improvements across the product lifecycle.
- Partner with DFT and design teams to implement SCAN, MBIST, SerDes, and functional test methods that maximize defect and parametric coverage.
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This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.