Ciena

Ciena

THW Client Co-op (January 2027 - Rochester, NY)

New York · Intern · Internship

Sponsorship not specified$27k-$38kDetected 27 days ago
PythonLinuxFPGAVHDLVerilogElectrical EngineeringCommunicationProblem SolvingWriting

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odds of building a lasting career here

32Risky
Cap-exempt (no lottery)0
Sponsors this role62
Entry-level history0
PERM / green-card track0
Lottery odds (Level I)39
Fits your clock70

Thin sponsorship signal and lottery-bound (~15% per draw). A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.

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Employer immigration record

from this employer's Department of Labor filings

Green-card filing pattern in this occupation

Context, not a finding about this posting: of this employer's 4 green-card filings in this occupation, 100% were for a worker who already held the job.

Files H-1B transfers

4 transfer filings in the last year, covering 4 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

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About the role

  • 4 month work term, starting January 2027
  • This role provides hands-on exposure to digital ASIC development, verification methodologies, prototype development, automation, and optical networking technologies.
  • Apply communications standards knowledge, including IEEE 802.3, ITU, and OIF specifications, within development activities.

Responsibilities

  • Join the ASIC IP team and contribute to the design and verification of client protocol mapping IP used in Ciena's WaveLogic coherent engine chipsets.
  • The position offers opportunities to build technical experience while contributing to defined engineering deliverables.
  • Design and verify digital blocks, cores, and subsystems for ASIC products and FPGA-based validation.
  • Collaborate with design and verification engineers on client subsystem and core development activities.
  • Implement digital designs using SystemVerilog, Verilog, and VHDL.
  • Develop and enhance prototype and development automation solutions.
  • At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.
  • Verify digital designs using SystemVerilog and UVM methodologies.

Requirements

  • Previous experience with ASIC or FPGA development, as well as knowledge of and experience using System Verilog, Verilog, VHDL and Python
  • Self-motivated, and the ability to work independently as well as in a team environment
  • Knowledge of OTN, Ethernet, and other Optical Networking standards

Skills

  • Strong verbal and technical writing skills
  • Strong problem solving and debugging skills

Compensation

  • The hourly pay range for this position is $27.00 - $37.50
  • Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business.
  • Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
  • In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.

Equal opportunity

  • If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

This listing is sourced directly from Ciena's careers page and normalized into a canonical job model.