Renesaselectronics
Staff Digital Design Engineer
Chandler, Arizona, United States · Staff+
Sponsorship not specifiedDetected 5 days ago
Product ManagementExcelVerilogElectrical EngineeringHardware DesignSignal ProcessingLeadershipMentoring
About the role
- In this role, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications.
- For more information, please read our Diversity & Inclusion Statement.
Responsibilities
- Integrating design at the top level and running block & top-level simulations.
- Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF.
- Support DFT strategy and implementation, and review test case development.
- Supporting analog team to develop AMS, System Verilog or Verilog-real behavioral models.
- Developing detailed block & chip level design documents and collateral.
- Holding and participating in key design reviews and completion of various checklists.
- Document device errata, develop work-around solutions, implement engineering changes when necessary.
- >10 years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management.
- Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design.
Requirements
- Perform silicon evaluation as required.
- Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
- Strong understanding of ASIC design methodology.
- Strong understanding of Lint, CDC & RDC tools.
- Strong understanding of block-level & chip-level verification techniques.
Nice to have
- experience with Digital Signal Processing (DSP) concepts and hardware realizations.
- experience with methodology and flow automation using appropriate scripting.
- experience with mixed-signal design methodologies.
- experience with STA and timing closure.
- experience with low-power design techniques, including clock and power gating (UPF).
- experience with power analysis and optimization.
- experience with advanced verification methodologies (UVM).
- experience with industry-standard protocols such as AMBA or I2C.
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