Astera Labs Inc.

Astera Labs Inc.

Principal Digital Design Engineer

San Jose, California, United States · Principal

Sponsorship not specifiedDetected 4 days ago
PythonExpressComplianceCadenceElectrical EngineeringCommunication

Stay score

odds of building a lasting career here

42Risky
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds40
Fits your clock70

Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.

Lottery odds assume a STEM candidate.

Personalize to your clock →

Employer immigration record

from this employer's Department of Labor filings

Green-card filing pattern in this occupation

Context, not a finding about this posting: of this employer's 5 green-card filings in this occupation, 100% were for a worker who already held the job.

Files H-1B transfers

28 transfer filings in the last year, covering 28 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

Community outcomes

No reports yet — be the first to help the next applicant.

About the role

  • The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.
  • We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers.

Responsibilities

  • Development/support for PCIe or Ethernet Switch products.

Requirements

  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Required Experience:
  • Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
  • Experience with Synopsys and/or Cadence digital design tools/flows
  • Silicon bring-up and debug expertise

Nice to have

  • Strong academic and technical background in electrical engineering.
  • A Bachelor's degree in EE is required, and a Master's degree is preferred.

Skills

  • Labs (NASDAQ:
  • ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
  • Discover more at www.asteralabs.com.

Compensation

  • The base salary range is $185,000.00 USD – $230,000.00 USD.

Visa & Work Authorization

  • Authorized to work in the US and start immediately.
Apply directly at Astera Labs Inc. →Create a free account for alerts like thisView Astera Labs Inc. immigration profile

This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.