Astera Labs Inc.
Tech Lead Engineer, Design Verification
San Jose, California, United States
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About the role
- As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments.
- Within CCE2, you will lead meaningful verification challenges from planning and testbench architecture through coverage closure and silicon learning. You will contribute to Astera Labs' hyper-growth mission by helping deliver highly reliable PCIe and UALink connectivity products that keep AI accelerators, memory, and compute resources operating at scale.
- As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure.
Responsibilities
- Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.
- Review designs and verification plans with architecture and RTL teams to identify corner cases early.
- Lead verification planning and execution for assigned features, tracking risks, milestones, and quality metrics.
- Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models.
- Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, UALink, and UCIe behavior.
- Partner with RTL and firmware teams to refine interfaces, improve observability, and resolve functional issues.
- Develop regression strategies and automation to improve test quality, turnaround time, and failure triage.
- Partner with design and post-silicon teams on issue isolation, root-cause analysis, and silicon bring-up readiness. <s
Skills
- Verification Strategy and Planning
- Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality.
- Environment Development and Execution
- Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration.
- Coverage, Quality, and Silicon Readiness
Benefits
- Drive functional and code coverage analysis, identify verification gaps, and close coverage to agreed milestones.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.