Etchedai

Power Optimization Engineer

Cupertino, CA

Sponsorship not specifiedDetected 118 days ago

NLPResearch

About the role

Correlate the estimated power consumption to the measured power.
We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Develop chip power model from chip architecture, estimate chip power from microarchitecture, and devise power saving techniques for product use cases.
Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to implement design for optimal power using advanced power management techniques.
Digital design and optimization using industry-standard power analysis tools and methodologies.
Relocation support for those moving to Cupertino
We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware.
Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

Experience in power optimization using dynamic voltage and frequency scaling techniques, power aware synthesis, glitch power reduction techniques as well as efficient power delivery network implementation.
Experience with gate-level power optimization through VCD-based and/or FSDB-based power analysis.
Strong understanding of concepts of energy consumption, estimation, data movement, low power design, and power-saving features.
You may be a good fit if you have
Strong candidates may also have experience with

We are a fully in-person team in Cupertino, and greatly value engineering skills.

This listing is sourced directly from Etchedai's careers page and normalized into a canonical job model.