Baya Systems
Hardware Verification Engineer
Santa Clara, California, United States
Sponsorship not specifiedDetected 475 days ago
PythonIntellectual PropertyVerilogElectrical EngineeringCommunicationCollaborationProblem Solving
About the role
- Baya Systems is inspired by the baya bird, also known as the weaver.
- Baya birds weave very unique and intricate hanging nests from different materials.
- The nests are robust and safe while being extremely lightweight and efficient.
Responsibilities
- Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems
- Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards
- Collaborate with software teams to define and implement configurable testbenches
Requirements
- Proficiency in Verilog, SystemVerilog
- Deep experience with UVM-based testbenches
- Experience with modern programming languages like Python
- BS, MS in Electrical Engineering, Computer Engineering or Computer Science
- 8+ years and current hands-on experience in block-level/IP-level/SoC-level verification
- Familiarity with industry-standard EDA tools for simulation and debug
- Knowledge of Arm AMBA protocols such as AXI, APB, and AHB
- Understanding of Arm CHI protocol is a plus
- Experience on working with IP's for caches, cache coherency, memory subsystems, interconnects, and NoC's
- Experience with formal verification techniques, emulation platforms is a plus
- Excellent problem-solving skills and attention to detail
- Strong communication and collaboration skills
Compensation
- Salary commensurate with experience
- Performance incentives
Benefits
- Work with design teams test plans, failure debug, coverage, etc.
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This listing is sourced directly from Baya Systems's careers page and normalized into a canonical job model.