University Talent
Intern - Characterization and Support
SAN JOSE · Intern · Internship
Sponsorship not specifiedDetected 14 days ago
PythonCadenceElectrical EngineeringTest AutomationCommunicationCollaborationProblem Solving
About the role
- This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering Intern.
Requirements
- Currently pursuing a Bachelor's or Master's degree in electrical engineering with 0-2 years of relevant work experience
- Ability to work collaboratively in a team environment
Nice to have
- Prior experience in the hardware semiconductor or electronics industry is a plus
- Experience with script-based test automation in Python, C or other scripting tools is a plus.
Skills
- Intern will be responsible for validating both system-level and electrical performance of internal silicon test chips.
- The intern will work cross-functionally to ensure product functionality, reliability, and successful deployment.
- Very good fundamentals in analog and digital electronics, RTL, Signal integrity, control systems.
- Strong analytical and problem-solving skills
Compensation
- Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
Benefits
- bonus, equity, and benefits.
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