Globalfoundries

Globalfoundries

Principal Engineer, Analog Design

USA - Texas - Richardson · Principal

Sponsorship not specified$10k-$15kDetected 7 days ago
PythonMATLABCadenceElectrical EngineeringCommunicationCollaborationMentoring

About the role

  • GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and
  • give customers the power to shape their markets. For more information, visit www.gf.com.

Responsibilities

  • Contribute to architecture discussions and design tradeoff analysis with senior team members
  • Perform transistor-level schematic design, simulation, and verification using industry-standard EDA tools
  • Work closely with layout engineers to ensure parasitic-aware design and performance closure
  • Support and contribute to design reviews and verification planning
  • Collaborate across disciplines including layout, verification, and SoC integration teams
  • Generate clear documentation for design specifications, simulations, and validation results
  • Mentorship of junior design/layout engineers in design best practices and effective collaboration

Requirements

  • Bachelor's or master's degree in electrical engineering or related field 10-15 years of experience in analog or mixed-signal IC design.
  • Experience with transistor-level design and simulation in CMOS technologies
  • Familiarity with industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.)
  • Ability to run and analyze simulations across PVT and variability conditions
  • Ability to work effectively in cross-functional, global teams

Nice to have

  • Experience designing one or more analog blocks from spec to simulation (partial or full ownership)
  • Exposure to silicon validation and lab debugging
  • Familiarity with layout concepts and parasitic effects
  • Experience with low-power design techniques
  • Exposure to advanced nodes such as Bulk CMOS, FDSOI, or FinFET
  • $153,000.00 - $265,000.00
  • Requests for accommodation will be considered on a case-by-case basis.
  • Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.

Compensation

  • Stability and compensation

Benefits

  • Perform all activities in a safe and responsible manner and support Environmental, Health, Safety & Security requirements and programs

This listing is sourced directly from Globalfoundries's careers page and normalized into a canonical job model.