Lumilens

Verification Lead (Lead DV)

San Jose

Sponsorship not specifiedDetected 28 days ago

Cloud PlatformsFPGAVerilogLeadership

About the role

As a founding hire you define the methodology before there's RTL to verify - this role is on the critical path, and getting the coverage strategy and regression infrastructure right early is the single biggest schedule lever we have.
The full DV strategy: verification plan, coverage model (functional + code), UVM architecture, and signoff criteria from block to full-chip.
Verification of the in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage.

Stand up regression/CI infrastructure and nightly runs before design hands over first RTL.
You own verification end to end for a first-of-its-kind chiplet.
Hardware-assisted verification: bring up and own the emulation / FPGA-prototyping methodology.
Professional development opportunities and certification support
Lead and grow the DV team (across FEC, UCIe, MCU, datapath, and full-chip).

About Lumilens
This isn't incremental innovation, it's a ground-floor opportunity to rethink the optical layer from the silicon up.

Comprehensive benefits package including health, dental, and vision
All qualified applicants will receive consideration without regard to race, color, religion, gender identity, sexual orientation, veteran status, disability, or any other legally protected status.
Deep UVM/SystemVerilog; coverage-driven verification; constrained-random methodology.
Regression/CI at scale (grid, triage automation), and rigorous coverage closure.

This listing is sourced directly from Lumilens's careers page and normalized into a canonical job model.