MatX
Silicon Design-for-Test (DFT) Engineer
Mountain View, CA · Senior · Contract
No sponsorship$120k-$275kDetected 40 days ago
Full-Stack DevelopmentMachine Learning
About the role
- This position requires access to information that is subject to U.S. export controls.
- MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings.
- No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.
Responsibilities
- Design and develop functional test solutions for SERDES PHY, covering loopback, eye diagram characterization, and margin testing.
- Perform DFT integration of PHY IP blocks, including boundary scan, BIST interfaces, and test mode control signals, and develop robust pattern porting flows from IP-level to SoC-level.
- Develop and maintain firmware loading flows for PHY bring-up and test - including SPI/JTAG-based firmware download, register initialization sequences, and debug support during test program development.
- Collaborate closely with verification, firmware, and test engineering teams to develop and bring up silicon test programs from simulation to ATE.
- Commute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done!
Requirements
- Hands-on experience with DFT implementation - MBIST, at-speed scan and scan compression.
- Strong knowledge of modern DFT standards and protocols: JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN).
Nice to have
- Experience or Working Knowledge of loading and validating PHY firmware via serial interfaces (SPI, I2C, or JTAG), including understanding of bootloader sequences and register map initialization.
- Solid experience integrating PHY DFT interfaces (e.g., SERDES PHY test modes, analog test buses into the SoC DFT architecture.
- Experience with system-level DFT access - hierarchical test access, test data compression, and multi-die/chiplet DFT - is a strong plus.
- Familiarity with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, or equivalent.
Compensation
- The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.
- Early Career - $120,000 - $275,000 + equity
- Mid Career - $175,000 - $450,000 + equity
- Senior Career - $275,000 - $600,000 + equity
- A Stake in our success A flexible cash equity compensation mix that fits your needs
- Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year
Benefits
- A Stake in our success A flexible cash equity compensation mix that fits your needs
- Health & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don't)
- Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood
- Learning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
- Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don't!
- Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
- MatX E[x]tras $50 per month to use on the perks you care about most
- Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year
- Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursement
Visa & Work Authorization
- All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.
This listing is sourced directly from MatX's careers page and normalized into a canonical job model.