Ambarella Corp.
ASIC Design Engineer II
US Headquarters · Mid · Full-time
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About the role
- Job Description
Responsibilities
- Design and implement video compression, image processing, vector processing, neural network accelerators, processor cores, and memory subsystems using Verilog and SystemVerilog.
- Perform logic design, implementation, and verification utilizing Verilog, SystemVerilog, and relevant programming and scripting languages.
- Synthesize and optimize RTL for performance, area, and power efficiency.
- Develop and enhance front-end design methodologies and tool flows.
Requirements
- Master's degree in Electrical, Electronics, or Computer Engineering, with 0-5 years of relevant experience.
- Proficiency in SystemVerilog, Verilog, and Perl.
- Experience with scripting languages and the ability to write assembly language programs.
- Master's degree in Electrical, Electronics, or Computer Engineering, with 0-5 years of relevant experience. Solid understanding of computer architecture, logic design, and VLSI design principles. Proficiency in SystemVerilog, Verilog, and Perl. Familiarity with design verification methodologies and functional coverage concepts. Experience with scripting languages and the ability to write assembly language programs. Strong communication skills and a collaborative, team-oriented mindset. Demonstrated problem-solving skills and analytical thinking. Knowledge of logic synthesis and timing closure is a plus.
- Why Join Us?
- Work on industry-leading products in an innovative and collaborative environment.
- Make a direct impact on technologies used in autonomous vehicles, smart cameras, and more.
- Competitive compensation, excellent benefits, and career development opportunities.
- The base range is $130,000 -$160,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits. Be a part of something extraordinary.
Nice to have
- Knowledge of logic synthesis and timing closure is a plus.
Compensation
- Competitive compensation, excellent benefits, and career development opportunities.
Benefits
- Analyze code and functional coverage metrics, and collaborate with the verification team to identify and address coverage gaps.
This listing is sourced directly from Ambarella Corp.'s careers page and normalized into a canonical job model.