d-Matrix
Sr. Staff Design Verification Engineer
Santa Clara · Staff+
Sponsorship not specifiedDetected 566 days ago
C++CLLMsVerilogElectrical EngineeringCollaborationProblem Solving
Stay score
odds of building a lasting career here
40Risky
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds40
Fits your clock70
Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.
Lottery odds assume a STEM candidate.
Personalize to your clock →Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- We've built the industry's first highly programmable in-memory computing architecture, applicable across a broad range of applications from cloud to edge.
- This is a unique opportunity to help shape a company at an early stage and grow into a future leader in an industry poised for global impact.
Responsibilities
- Develop and execute verification plans across the SoC/IP verification cycle, from architecture definition through tape-out and silicon bring-up
- Build and maintain UVM/OVM-based verification environments for complex ASIC/SoC designs
- Drive root-cause analysis and debug of verification failures in close collaboration with design and architecture teams
- Partner cross-functionally with design, architecture, and physical design teams to align verification strategy with tape-out schedules
- Contribute to the evolution of verification methodology and infrastructure to support next-generation in-memory computing architectures
- Hands-on ASIC/SoC design verification test development and debug experience
Nice to have
- Experience with C/C++ and SystemC
- Track record leading the creation and implementation of multiple SoC verification environments and driving tape-out efforts
- BS in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience (MS preferred with 7+ years)
Benefits
- Write and debug SystemVerilog testbenches, leveraging randomization, functional coverage, and assertion-based methodologies
- Define and track coverage closure goals to ensure comprehensive verification sign-off
- Fluency with SystemVerilog (randomization, constraints, coverage, assertions) and verification methodologies such as UVM/OVM/VMM
Company info
- At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology.
- We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible.
- Our culture is one of respect and collaboration.
- We value humility and believe in direct communication.
- Our team is inclusive, and our differing perspectives allow for better solutions.
- We are seeking individuals passionate about tackling challenges and are driven by execution.
- Ready to come find your playground?
- Together, we can help shape the endless possibilities of AI.
- d-Matrix is building a company and culture designed to last - one grounded in transparency, inclusiveness, and intellectual honesty, where continuous learning is part of the job.
Equal opportunity
- Employment Policy
- d-Matrix is proud to be an equal opportunity workplace and affirmative action employer.
- We're committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work.
- We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
Apply directly at d-Matrix →Create a free account for alerts like thisView d-Matrix immigration profile
This listing is sourced directly from d-Matrix's careers page and normalized into a canonical job model.