Altera

Altera

EDA Technical Program Manager

San Jose, California, United States · Senior

Sponsorship not specified$167k-$241kDetected 12 days ago
Project ManagementAgileJiraConfluenceProcess ImprovementCadenceFPGAElectrical EngineeringLeadershipCommunicationCollaborationMentoringPublic Speaking

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odds of building a lasting career here

61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.

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Employer immigration record

from this employer's Department of Labor filings

Green-card intent detected

Altera Corporation obtained a prevailing wage determination for Electronics Engineers, Except Computer in San Jose, CALIFORNIA on 2026-06-10. No matching green-card filing appears in our data yet. The determination expires in 2 days (2026-09-07), and a green-card filing must follow before then or the employer starts over.+2 more active determinations on file

Files H-1B transfers

13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

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About the role

  • At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
  • The Senior EDA TPM will have broad ownership of programs spanning multiple engineering organizations and will be responsible for driving programs from strategy and definition through execution, delivery, and operationalization.
  • The ideal candidate brings a strong combination of technical program management leadership, semiconductor/EDA domain expertise, and demonstrated experience leading large, highly complex engineering programs.

Responsibilities

  • Lead end-to-end execution of highly complex, strategic technical programs supporting EDA, Physical Design, CAD, semiconductor development, and next-generation FPGA technologies.
  • Own program strategy, scope, objectives, success criteria, execution plans, milestones, dependencies, and delivery commitments across multiple engineering organizations.
  • Partner closely with senior engineering leaders and architects to translate business and technical objectives into executable program strategies and roadmaps.
  • Drive cross-functional execution across Physical Design, CAD/EDA, Software Engineering, Architecture, RTL Design, Verification, Validation, Product Engineering, and other engineering organizations.
  • Lead programs involving significant technical complexity, organizational dependencies, resource constraints, evolving requirements, and competing priorities.
  • Establish and maintain integrated program plans encompassing schedules, milestones, critical paths, dependencies, resource requirements, deliverables, and risk mitigation strategies.
  • Identify critical technical and organizational risks early, develop mitigation strategies, and drive issues to resolution with appropriate stakeholders and leadership.
  • Influence senior technical stakeholders and engineering leaders without direct authority to drive alignment, accountability, and timely execution.
  • Partner with engineering management to assess resource requirements, staffing constraints, technical priorities, and tradeoffs necessary to meet program commitments.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Engineering Management, or a related technical discipline, and 10+ years of relevant experience
  • or Master's degree in a related field and 8+ years of relevant experience.
  • 10+ years of experience in Technical Program Management, Engineering Program Management, or a related technical program leadership role.
  • 8+ years of experience managing complex, cross-functional technical programs within the semiconductor, FPGA, ASIC, EDA, hardware, software, or related technology industry.
  • 8+ years of experience managing program schedules, milestones, critical paths, dependencies, risks, and deliverables across multiple engineering teams.
  • 5+ years of experience working directly with semiconductor development, EDA, CAD, Physical Design, or related engineering organizations.
  • 5+ years of experience presenting program status, risks, schedules, and execution plans to engineering leadership and/or executive stakeholders.
  • 5+ years of experience using program/project management tools such as Jira, Confluence, Microsoft Project, Smartsheet, or equivalent platforms.
  • Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, Engineering Management, Business Administration (MBA), or a related technical field.
  • 10+ years of experience specifically within the semiconductor, FPGA, ASIC, EDA, CAD, or electronic design automation industry.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Engineering Management, or a related technical discipline, and 10+ years of relevant experience; or Master's degree in a related field and 8+ years of relevant experience.
  • Direct experience supporting Physical Design, CAD/EDA, Design Automation, or semiconductor implementation organizations.
  • Strong understanding of Physical Design methodologies, including floorplanning, placement, routing, clock tree synthesis, timing analysis and closure, signal integrity, power optimization, physical verification, design implementation, and design convergence.
  • Experience managing programs involving EDA tool development, tool qualification, flow development, methodology development, design infrastructure, or engineering productivity initiatives.
  • Experience leading programs across the full semiconductor development lifecycle, from architecture and design through implementation, verification, validation, and productization.

Skills

  • About Altera

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $166,900 - $241,000 USD

Benefits

  • Develop executive-level reporting and communication that clearly articulates program health, accomplishments, risks, dependencies, resource constraints, decisions required, and recovery plans.
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