Altera

Altera

Principal Engineer, Design Verification - DDR Memory Subsystems

San Jose, California, United States · Principal

Sponsorship not specified$210k-$299kDetected 25 days ago
PythonAlgorithmsCI/CDProduct ManagementFPGAVerilogElectrical EngineeringLeadershipCommunicationMentoring

About the role

  • This individual will serve as the technical expert for memory subsystem verification, driving verification architecture, methodology, execution, and quality across multiple product generations.

Responsibilities

  • Serve as the technical lead for Design Verification of complex DDR memory subsystems across multiple FPGA product families.
  • Define and drive verification architecture, methodology, and strategy for DDR controllers, PHYs, training logic, calibration flows, and memory subsystem integration.
  • Partner closely with Architecture, RTL Design, Physical Design, Firmware, System Validation, and Silicon Engineering teams throughout the product lifecycle.
  • Lead root-cause analysis of complex subsystem integration, timing, protocol, and performance issues.
  • Influence memory subsystem architecture by providing verification-driven feedback during early design phases.
  • Mentor senior verification engineers while establishing organization-wide Design Verification best practices.
  • Drive continuous improvements in verification infrastructure, automation, CI/CD workflows, regression efficiency, and reusable IP verification methodologies.
  • Support post-silicon bring-up, characterization, and system validation activities to ensure successful product deployment.
  • At Altera, you'll help define the future of programmable computing by developing the memory subsystem technologies that power next-generation AI, cloud, networking, and edge applications.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline.
  • 10+ years of experience verifying DDR memory subsystems, including memory controllers and PHY architectures.
  • Strong knowledge of:
  • Proven experience verifying high-performance memory interfaces within large SoC or FPGA environments.
  • Excellent communication skills with the ability to influence technical direction across cross-functional engineering organizations.
  • We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
  • Applicants must be eligible for any required U.S. export authorizations.
  • 15+ years of Design Verification experience developing complex ASIC, SoC, or FPGA products.
  • Extensive expertise with SystemVerilog, UVM, SystemVerilog Assertions (SVA), constrained-random verification, functional coverage, and verification planning.
  • LPDDR4
  • LPDDR5
  • HBM/HBM2/HBM3

Nice to have

  • Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
  • Experience verifying additional high-speed interfaces such as PCIe, Ethernet, CXL, UCIe, HBM, or SerDes.
  • Experience with formal verification methodologies and formal property checking.
  • Experience with emulation platforms, FPGA prototyping, and post-silicon validation.
  • Proficiency with scripting languages such as Python, Perl, Tcl, or Shell for automation and infrastructure development.
  • Experience implementing CI/CD pipelines and scalable regression frameworks.
  • Experience mentoring senior engineers and serving as the technical authority for complex verification programs.
  • Shift 1 (United States of America)

Skills

  • About Altera

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • $209,500 - $299,200 USD

Benefits

  • Develop comprehensive verification plans utilizing constrained-random verification, assertions (SVA), functional coverage, scoreboarding, protocol checking, and regression automation.
  • Drive verification closure through rigorous coverage analysis, debug methodologies, and metric-based execution.
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