Astera Labs Inc.
Senior Principal Test Engineer
San Jose, California, United States · Principal
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DOL prevailing wage, 2026-27 wage year · Software Quality Assurance Analysts and Testers (15-1253) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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About the role
- Astera Labs is seeking a Senior Principal Test Engineer to serve as a technical authority for test engineering across complex mixed-signal silicon and high-speed connectivity products.
- This role is central to delivering reliable, scalable connectivity for rack-scale AI infrastructure.
Responsibilities
- Define and own comprehensive test strategies, specifications, and plans from product definition through high-volume production.
- Partner with design and product engineering teams to identify testability requirements and make effective design-for-test tradeoffs.
- Architect tester solutions and guide development of Tester HW design to meet specific and roadmap of products
- Validate Tester Designs and characterize before implementing into Mass Production.
- Lead root-cause analysis and yield improvement using protocol analyzers, oscilloscopes, manufacturing data, and structured failure analysis.
- Serve as a senior technical advisor across test, DFT, design, operations, quality, and external manufacturing organizations.
- You will define Test strategies for SCM High Volume Manufacturing and Validation Boards shipped to customer development and own execution from early product engagement through high-volume manufacturing.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12-20 years of experience in Test engineering or Product Engineering from development through high-volume manufacturing.
- Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB.
- Experience with Test SW development, production debug, and test-time optimization.
Nice to have
- Master's or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Experience with Electrical HW board design on complex Test HW implementation.
- Strong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, along with control interfaces such as I2C, I3C, SPI, MDIO, and JTAG.
- Proficiency in C/C++ or Python for ATE programming, data processing, and test automation
- familiarity with databases and yield analytics.
- Proficient in Mandarin Chinese.
Skills
- Test Strategy and Product Ownership
- Technical Leadership and Cross-Functional Execution
- Mentor engineers, influence technical decisions, and communicate risks, tradeoffs, and recommendations to cross-functional stakeholders.
Compensation
- The base salary range is $205,000 USD - $260,000 USD.
Benefits
- Establish coverage, quality, yield, test-time, and cost objectives, and drive measurable improvements across the product lifecycle.
- You will influence product quality, coverage, yield, test cost, and time to market while partnering with design, DFT, product engineering, operations, and manufacturing teams in a fast-moving, hyper-growth environment.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.